The Video Generation Board

 

U18, 19 & 20 form the interface between Video RAM and the CPU. When Cacc is enabled, the CPU is connected to VRAM. Likewise U16 & 17 buffer the video address counter with VRAM. These are enabled by Vacc.

U9 & U10 form a 13 bit asynchronous counter, clocked from the S2 signal. U7 and U8 decode the output of this counter and convert it into the address of either a bitmap or an attribute depending on whether S1 is high or low. This then gets fed to the Video RAM through U16 & 17 on a Vacc cycle.

U4, 5 & 6 form an 8 bit shift register. These three components can be directly replaced by a 74HC166 if available. On an S1 state, the shift register is loaded with the byte in memory being pointed to be the address counter. On each pulse of the 7MHz, the shift register moves the bitmap right 1 bit and outputs the most significant bit to the SOUT line.

U2 and U3 control the output of the attribute byte. on an S0 state, the attribute is fetched from memory and stored U2 prior to being displayed. Then on the S1 state, corresponding to start of a new bitmap byte, this attribute is transfered to U3 for outputting.

U11, U12D and U13D control the flash attribute. If the flash bit in the attribute byte is set, the SOUT byte is XOR'd with the output of the 'HC4040 counter (U11) inverting it for 32 out of every 64 frames.

U14 and U15 (4 to 1 line decoders) create the video output. Depending on the state of the SOUT and Video Enable lines, they select either the border colour (BDR0,1 & 2), the INK, or the paper colour from the attribute byte on S3.

The resistor/diode network on the other side of U14/15 interface the circuit to an analogue RGB monitor. When BRIGHT is low, the diodes conduct so the monitor sees a voltage divider circuit of the 470 & 150 Ohm resistors. When Bright goes low, the diodes stop conduction so the monitor only sees the 470Ohm.

Finally, U13D XORs the Vertical and Horizontal Sync to generate a composite sync signal.

Circuit Diagram

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